1. Field of the Invention
This invention relates to testing of integrated circuits and board level systems including integrated circuits, and more specifically to built-in self-testing of signal propagation delays for such integrated circuits and integrated circuit systems.
2. Description of the Prior Art
Due to increased complexity of integrated circuits (ICs) and reduced access to internal circuit nodes, properly testing such devices has become a major bottleneck during their prototyping, development, production and maintenance. Hence there has arisen the field of built-in self-test wherein circuitry which is intended solely to support testing is included in an integrated circuit and/or in a system including integrated circuits.
For synchronous, "random" logic in digital ICs and IC systems (boards), prior art built-in self test (BIST) schemes detect signal delays using at-speed scan test; for logic related to the pin interface circuitry located at the periphery of the IC, boundary scan is applied at or below the normal clock rate; and for memories such as SRAM, DRAM and ROM special patterns are applied at the normal operating clock rate.
However, many IC signal paths which can contain delay faults are not covered by prior art BIST: these include unclocked combinational logic, asynchronously clocked logic, and gated-clock logic (e.g. ripple counters); paths from an input pad to an output pad; paths which include a tri-state output enable/disable delay, and set-up and hold times.
In addition, due to natural variations in the manufacturing process, some ICs have shorter delays than others, and these faster ICs can be sold at a premium price. Sorting or "binning" of ICs by their performance is often done by measuring the delay in critical paths. These paths are tested by applying a sequence of test patterns to the IC until the delay path of interest in the IC has been "sensitized" such that one additional signal transition on an input pin will cause a signal to propagate through the path of interest to an output pin, whereupon the delay can be measured using off-chip automatic test equipment (ATE). The measurement of delays to accuracies of less than one nanosecond (ns) requires expensive circuitry in ATE at every pin of the IC, so that a delay between any two pins can be measured. This precise timing is a significant contributor to the cost of ATE.
In such timing tests, the tester initiates a measurement by supplying a stimulus waveform to the delay path under test, and then detects when the output of interest has responded. Generally, ATE measures delays by applying a test pattern and detecting whether a selected output signal has an expected value at a precise instant in time; if it does not, then the test pattern is applied again and the output is observed at a different instant in time; this process continues using a binary search until the output signal transition time is bounded by arbitrarily close points in time. The procedure requires accurate time delays in the ATE for placement of the timing edge which samples the circuit's output value. Sometimes the input signal activates two outputs, and the difference in output delays is the important value to be measured. In this case, both delays are measured by the ATE, and one is subtracted from the other. Other equipment is able to measure delay differences by counting high speed clock pulses between the two events and by using analog interpolation between clock pulses.
Another method sometimes used to "bin" ICs according to the delays, is to use a representative logic circuit, namely a ring oscillator on the IC, and measure its frequency of oscillation. A ring oscillator is a chain of inverters or other logic gates permanently connected in a ring or loop, in which the total number of inversions in the loop is odd thus ensuring oscillation, and the loop oscillates at a frequency inversely proportional to the delay around the loop.
It has also been proposed by Arabi & Kaminska in "Oscillator Test Strategy For Analog And Mixed Signal Integrated Circuits", VLSI Test Symposium, May 1996, pp. 476-482, that a useful test of analog circuits is to connect the analog circuit's output to its input, via an inverting and/or amplifying circuit (typically, specially designed for each circuit to be tested), to create an oscillator. The feedback circuit is designed such that the oscillation frequency is the maximum that can be achieved by the circuit under test, if it has correct gain and bandwidth. By comparing its oscillation frequency to the expected oscillation frequency, as determined by computer simulation or statistical experiment, the presence of analog defects can be detected.
In another area of delay evaluation, but not typically used for testing, a delay lock loop is used to make a delay path have the same delay as an input, e.g. one clock period. Using feedback, differences between the source delay and the controlled delay cause the control voltage for the controlled delay to change until the controlled delay is correct. The control voltage also controls other delay paths to make them have the same delay (or a ratio thereof). A delay lock loop does not measure delay, but copies it from a repetitive signal for use with other signals.
U.S. Pat. No. 4,875,201 issued Oct. 17, 1989 to Dalzell discloses a timed measurement apparatus including a delay line having accurate delay elements and a plurality of taps, each tap having an associated latch. The arrangement causes oscillation of the delay line in the presence of the first condition of the input signal. The counter counts the oscillations of the delay line, and the latches are caused to operate simultaneously in the second condition of the input signal. This is used for measuring qualities of the signals in a computer network for instance. This disclosure is incorporated herein by reference in its entirety.
U.S. Pat. No. 5,083,299 issued Jan. 21, 1992 to Schwanke et al. discloses a tester for measuring the time with which a signal propagates through an electronic component and which is comprised of a ring oscillator in which pulses are periodically generated and propagated around a loop. Within this loop, a fixture is disposed for selectively holding the electronic component that is to be tested, or a shorting plug, in a removable fashion. Pulses from the ring oscillator propagate through the fixture, and their period reflects whether the component/shorting plug is being held. Coupled to the loop is a timing circuit which generates a timing signal each time it receives a predetermined number of the pulses on the loop. Using this timing signal, the signal propagation delay through the electronic component is determined substantially more accurately than that which is obtainable by measuring propagation delay through the component directly. This disclosure is also incorporated herein by reference in its entirety.